1. Field of the Invention
The present invention relates to a semiconductor device that includes a capacity element for analog circuit, such as a semiconductor device with a structure in which a capacitance for analog circuit is added on a digital circuit, and a method for manufacturing such a device. More specifically, the present invention relates to a semiconductor device having a digital circuit, where a smaller capacity element (analog capacity element) of applied-voltage dependent is added on a DRAM-consolidated logic circuit having a DRAM mounted on a logic circuit, and a method for manufacturing such a device.
2. Description of the Related Art
In recent years, there is the growing need for configuring a semiconductor device to include a consolidated circuit with required circuit elements of two or more types on the same chip for accomplishing all functions. Examples of such a device are a product with a DRAM mounted logic circuit (DRAM-consolidated logic circuit) or a product with a flash-memory-mounted logic circuit (flash memory consolidated logic circuit), which is designed in many different types for its particular application or purpose.
Some DRAM-consolidated circuits require the formation of a capacity element with less applied-voltage dependency (analog capacity element) than that of DRAM cell capacitors in addition to an element to be used for structuring a digital circuit. The analog capacity element requires extremely less applied-voltage dependency than that of DRAM cell capacitors, so that a so-called MOS capacitor constructed of a silicon substrate and gate electrodes cannot be used as an analog capacity element because of its inherent voltage dependency. Regarding a capacitor that makes up a memory cell of DRAM, which has a thick capacity insulating film, for example as shown in FIG. 1, it cannot be used in an along capacity element because of its not enough small applied-voltage dependency.
For manufacturing some DRAM-consolidated logic circuits on which analog capacity elements are mounted, therefore, there is the need for forming a capacity element having a structure to be used in an analog circuit in addition to a general capacity element that makes up a digital circuit when the process.
For example, the element structure shown in a schematic diagram of FIG. 2 has been adapted in the DRAM-consolidated circuit product having the conventional analog capacity element. We will simply describe its manufacturing method and its configuration as follows. As shown in FIG. 2, an analog capacity element is configured as a MIM-type plate capacity element that is a capacity insulating film 10 sandwiched between a lower electrode 5 made of polysilicon and an upper electrode 12 made of polysilicon. For providing electric insulation with the other elements, for example, the lower electrode 5 is formed on a semiconductor substrate 1 having a diffusion layer region 3 and an element separation 2 so that the lower electrode 5 is formed on the same layer as that of the gate electrodes 4.
In a DRAM cell part, on the other hand, a bit line 11 is formed on an interlayer insulation film 8 and an accumulation electrode 14 is formed on a second interlayer insulation film 16 formed on a bit line 11. These electrodes in the DRAM cell part which are a bit line 11 and an accumulation electrode 14 are constructed on upper positions with respect to the analog capacity element. The DRAM cell capacitor consists of the accumulation electrode 14, a dielectric film 18 and the cell plate 19.
Next, we will briefly describe the process of forming the structure shown in FIG. 2 with reference to cross partial views of the respective steps in FIGS. 3 to 7.
At first, a silicon oxide film in thickness of about 7 nm as a gate insulating film 1a is layered on a silicon substrate 1 having an element separation 2 and a gate polysilicon film 15 in thickness of about 150 nm as a gate electrode 4 is layered on a silicon oxide film 1a. Subsequently, a silicon oxide film in thickness of about 50 nm to be used as a dielectric film 10 of an analog capacity element and, a doped polysilicon film in thickness of about 150 nm to be used as an upper electrode 12 are layered one after another. After that, both the doped polysilicon film provided as the top film and the silicon oxide film are subjected to the step of patterning, so that they are provided as the upper electrode 12 of the dielectric film 10 of the analog capacity element shown in FIG. 3.
Next, as shown in FIG. 4, the gate polysilicon film 15 is patterned to form a gate electrode 4 of a DRAM cell part and a lower electrode 5 of the analog capacity element, respectively. Then, the gate electrode 4 is used as a mask to form a diffusion layer region 3 by performing an ion-implantation of n-type impurity such as phosphorus into a source region.
Next, as shown in FIG. 5, an interlayer insulation film 8 that covers the formed analog capacity element is formed, such a manner that the insulation layer is layered entirely so as to be formed as one having a height of about 600 nm from the diffusion layer region 3 (about 250 nm from the top electrode 12). Subsequently, a connection hole 7 for obtaining an electrical connection between a bit line and the diffusion layer region 3 under the bit line by etching the interlayer insulation film 8 and the gate insulating film 1a. 
After forming a side-wall insulation film 9 in the connection hole 7, as shown in FIG. 6, films, such as a doped polysilicon film having a thickness of about 100 nm at a flat surface thereof is formed on a full surface of the interlayer insulation film 8, and subsequently, for example, a tungsten siliside film in thickness of about 100 nm is formed thereon. The above connection hole 7 is filled with the doped polysilicon and tungsten siliside films, and then subjected to the step of patterning using a technology of photolithography to form a bit line 11 after removing undesired parts of the doped polysilicon and tungsten siliside films by means of etching.
Next, as shown in FIG. 7, the second interlayer insulation film 16 is formed on the interlayer insulation film 8 at a height of about 300 nm from the top of the bit line 11. For connecting between the accumulation electrode 14 and the diffusion layer region 3 provided as a under layer thereof, a capacitor connecting hole 17 cutting through the second interlayer insulation film 16 and the interlayer insulation film 8 is formed by means of etching. Therefore, the depth of the capacitor-connecting hole 17 is about 1,100 nm.
After that, a side-wall insulation film 13, such as one having a thickness of about 50 nm is formed on the above capacitor connecting hole 17, followed by entirely layering a phosphorus doped polysilicon film, such as one having a thickness of about 70 nm at a flat surface. The above capacitor connecting hole 17 is imbedded in the phosphorus doped polysilicon and then subjected to the steps of patterning and etching to perform the processing operation on the accumulation electrode 14. After that the dielectric film 18 of DRAM cells and the cell plate 19 are formed, obtaining the structure shown in FIG. 2.
Conventionally, like an element configuration as shown in FIG. 2, the manufacturing process are divided into two different processes, one is to form an analog capacity element and the other is to form a DRAM cell part after the first one. The analog capacity element and the DRAM cell part cannot be formed simultaneously, because the thickness of the analog capacity insulating film 10 must be thicker than that of the DRAM capacity insulating film 18. As a consequence, the number of steps is increased.
While a non-flat surface of the analog capacity element is obtained because of its projected portions, caused by a dielectric film 10 and an upper electrode 12 of the capacity element. Therefore, the patterning the resist before the etching the gate electrodes has troubles.
Besides, it greatly impairs the advantage of making the resist patterning before the gate etching easily by forming the structure of an element separation 2 so as to make a flat surface of the substrate. Therefore, it is desirable to be able to solve such problems and to provide, the element configuration that takes the advantage of selecting the structure of element separation that allows a flat surface of the substrate without substantially increasing the number of steps when the analog capacity element is added to the DRAM-consolidated logic circuit.
The present invention aims to solve the problems described above and the purpose of the present invention is to provide a semiconductor device that includes a capacity element for an analog circuit, for example to provide an element configuration allowing that there is no substantial increase in the number of the steps for a semiconductor device having the configuration in which a logic circuit and a DRAM cell circuit are consolidated together, on which an analog capacity element is installed, compared with a semiconductor device having the configuration in which a logic circuit and a DRAM cell circuit are consolidated together as an analog capacity element is installed. More concretely, the present invention aims to provide: an element configuration that allows the resist patterning step accompanying with the steps of forming films and etching the films at the time of forming a dielectric film and electrodes on the top and bottom of such a dielectric film without substantially increasing the number of the steps; and a method for manufacturing an analog capacity element having such an element configuration. Furthermore, the present invention aims to provide an element configuration that allows a structure of element separation to be mounted in the substrate without spoiling the advantage of a flat surface of the substrate.
The present inventors found that the possibilities of adapting a conductive material, which is utilized in the formation of a bit line or an accumulation electrode, as an upper electrode that constitutes an analog capacity electrode and also adapting a material, which is utilized for a dielectric film 10 that constitutes an analog capacity element as a side-wall insulating film 9 or a side-wall insulating film 13. Regarding the analog capacity element, furthermore, we found that the structure in which the analog capacity element is imbedded into the interlayer insulation film is not necessarily required for attaining no substantial differences in the operation characteristics of the semiconductor device itself as far as that ins insulated from the DRAM cell part. For example, a third insulation film that electrically isolates a side wall of an accumulation electrode is utilized for a capacitor portion of a DRAM cell is formed on a position above the second interlayer insulation film while an accumulation electrode is used as a lower electrode of the capacitor. We concluded that the electric isolation could be attained comparing favorably with the configuration of the analog capacitor element imbedded in the interlayer insulation film if the analog capacity element was covered with such a third insulation film.
As a result of inventing a new element configuration on the basis of the above findings, we found that the analog capacity element did not show its bias dependency of the capacitance without any difference in the characteristics of DRAM cell itself if the under electrode 5 of the analog capacity element is provided on the same layer as that of the gate electrode 4 of the DRAM cell, the dielectric film 10 of the analog capacity element is positioned on the same layer as that of the side-wall insulation film 9 of the DRAM cell provided on the connection hole side wall on which the bit line is formed or the side wall insulation membrane 13 of the DRAM cell provided on the capacitor connection hole side wall of the accumulation electrode, and the upper electrode 12 of the analog capacity element is provided on the same layer as that of the conductive material 11 used for the formation of bit line or the conductive material 14 used for the formation of accumulation electrode. In addition, we confirmed that the installation of analog capacity element became possible without a substantial increase in the number of the steps if the above configuration was adapted. Furthermore, we complete the present invention on the basis of our findings that the advantages of such a configuration could be applied in broader range of the applications for the semiconductor device including the analog capacity element.